There is a case where packets are relayed by relay devices, or switches, from a packet transmission source device to a packet transmission destination device.
FIG. 1 is a diagram illustrating an example of a relay device. The relay device 1 depicted in FIG. 1 includes an administration module 2, interface cards 3 (3a to 3c), and switch circuits 4 (4a and 4b). The interface card 3 inputs and outputs user data. The switch circuit 4 performs switching according to a destination of a packet which is received from the interface card 3. That is, the switch circuit 4 selects an interface card 3 to which the packet is to be outputted, according to the destination of the received packet, and outputs the packet to the selected interface card 3. The administration module 2 administrates a state of the relay device 1 and outputs control information to the switch circuits 4 and the interface cards 3.
The relay device 1 depicted in FIG. 1 includes two sheets of switch circuits 4 so as to deal with a failure occurrence and planned replacement of devices. In the relay device 1 that uses a plurality of switch circuits 4 for redundancy as depicted in FIG. 1, the switch circuits 4 are synchronized with each other so that the working switch circuit 4 is switched, for example, in a case where a failure has occurred. However, the switch circuits 4 may lose synchronization among the switch circuits 4 due to various causes. For example, in a case where the switch circuits 4 respectively have their own clocks, even though the same frequency is set to all the clocks, difference in frequencies may be made among the switch circuits 4 due to deviation among the clocks.
FIGS. 2A and 2B are diagrams each illustrating an example of an operation when synchronization is lost between two switch circuits. In FIGS. 2A and 2B, synchronization has been lost between the switch circuit 4a and the switch circuit 4b. In both cases of FIGS. 2A and 2B, it is assumed that a clock frequency of the switch circuit 4a is higher than a clock frequency of the switch circuit 4b. Further, in FIGS. 2A and 2B, the interface cards 3a to 3c are each depicted redundantly on both the input (ingress) side and an output (egress) side for convenience of explanation. FIGS. 2A and 2B are depicted so as to facilitate visualization of the drawings, and interface cards 3 given the identical reference character are physically one interface card 3. For example, the interface cards 3a are depicted on both of the input side and the output side, but these interface cards 3a indicate physically one interface card 3a. Further, in FIGS. 2A and 2B, for convenience of explanation, packets are depicted with packet numbers indicating an order in which the packets are received by the relay device 1. Packets with the identical number indicate the same packet.
After the interface card 3a duplicates a received packet to obtain two packets, the interface card 3a outputs one packet to the switch circuit 4a and outputs the other packet to the switch circuit 4b. During a time period in which no congestion is occurring, even when processing in the switch circuit 4b is delayed compared to processing in the switch circuit 4a, the delayed processing of the switch circuit 4b is completed before a packet to be processed next is inputted into the switch circuit 4b. Therefore, packets to be processed by the switch circuit 4a and packets to be processed by the switch circuit 4b are the same packets, as depicted in FIG. 2A.
However, when congestion occurs, processing on a next packet is started in the switch circuit 4a before delay in processing in the switch circuit 4b is recovered. Therefore, when a congestion state is continuing, the timing of reading out packets from a buffer by the switch circuit 4a having a faster clock gradually precedes that by the switch circuit 4b, resulting in a state that packets to be processed in the switch circuit 4a and packets to be processed in the switch circuit 4b are different from each other. In the example of FIG. 2B, the switch circuit 4a outputs the 16th packet to the interface card 3a, while the switch circuit 4b outputs the 14th packet to the interface card 3a. When the switch circuit 4 in an active state is switched in such an asynchronous state, duplication or loss of a packet may occur. For example, in FIG. 2B, when the switch circuit 4a is active and is switched to the switch circuit 4b, a destination communication device receives the 14th and 15th packets from the switch circuit 4b. However, the destination communication device has already received the 14th and 15th packets which are switched by the switch circuit 4a. Accordingly, the destination communication device redundantly receives the 14th and 15th packets.
Meanwhile, it is assumed that the switch circuit 4b is active and is switched into the switch circuit 4a. In this case, output of the 14th and 15th packets from the switch circuit 4a has already been completed. Therefore, the switch circuit 4a does not transfer the 14th and 15th packets to the destination communication device after being set to be active, but the destination communication device has not received the 14th and 15th packets from the switch circuit 4b. Accordingly, loss of packets occurs in the destination communication device due to switching of the switch circuits.
In order to avoid such duplication or loss of data, an asynchronous transfer mode (ATM) exchange which synchronizes cell flows of redundant switches by using a test cell has been devised. This ATM exchange monitors cells inputted and inserts a test cell instead of a vacant cell when switching switches. The ATM exchange extracts a test cell from a cell outputted from a switch and acquires the output time of the test cell. When the output time of the test cell is different between switches, the ATM exchange performs control of causing a switch of which output time of a cell is earlier to delay output of a cell. Thereafter, when switches become synchronized, the ATM exchange switches the switches.
Further, as a related technique, such method has been devised that high-priority cells are inputted into a buffer provided for a switch of a standby operation system so as to avoid loss of the high-priority cells even when switches are switched due to a failure occurrence. Further, such method has been proposed that queue selection is performed for the number of stored cells which are stored in a buffer of a switching part of an active system so as to match a cell-storing state and a queue-selecting state of a switching part of the active system with those of a backup system. Further, such method has also been proposed in which voice processing blades share the reference timing and time information for voice processing, the voice processing is performed in synchronization with the reference timing to supply a synchronized packet, and system switching is performed in accordance with the time information.
Japanese Laid-open Patent Publication Nos. 5-56065, 3-135135, 2009-212724, and 2010-74629 are examples of related art.